1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to a semiconductor integrated circuit including a power-on reset circuit which resets an internal circuit in a semiconductor memory device during a start-up process of the semiconductor integrated circuit. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-51894 filed on Feb. 26, 2004, which is herein incorporated by reference.
2. Description of the Related Art
FIG. 1 is a block diagram for describing a semiconductor integrated circuit in a semiconductor memory device of the related art. The semiconductor integrated circuit comprises a power-on reset circuit 100, an internal voltage generating circuit 200, a control circuit 300 and an internal clock generating circuit 400. A power supply voltage Vcc is externally input to the power-on reset circuit 100, the internal voltage generating circuit 200, the control circuit 300 and the internal clock generating circuit 400. Also, a clock signal ECLK is externally input to the internal clock generating circuit 400.
During a start-up process of the semiconductor integrated circuit, the power-on reset circuit 100 generates a power-on reset signal POR based on the power supply voltage Vcc. The power-on reset signal POR is input to the internal voltage generating circuit 200 and the control circuit 300. The power-on reset circuit 100 has circuitry as shown in FIG. 2A and outputs the power-on reset signal POR from an output terminal TPOR. The power-on reset circuit 100 has PMOS transistors P1–P5 which receives the power supply voltage Vcc and NMOS transistors N1–N5 which receives a ground voltage Vss. The PMOS transistors P1–P2 and the NMOS transistor N1 are coupled to a first node nd1 and the PMOS transistors P3–P5 and the NMOS transistors N2–N5 are coupled to a second node nd2. The power-on reset circuit 100 also has two inverters coupled in series between the second node nd2 and an output terminal TPOR. The power-on reset signal POR is output from the output terminal TPOR of the power-on reset circuit 100. The internal voltage generating circuit 200 generates an internal power supply voltage IVcc based on the power supply voltage Vcc for itself and the control circuit 300. The internal voltage generating circuit 200 is reset by the power-on reset signal POR. The internal clock generating circuit 400 generates an internal clock signal ICLK for the control circuit 300 based on the power supply voltage Vcc and the external clock signal ECLK. The internal clock generating circuit 400 includes a phase-locked loop circuit (hereinafter referred to as “PLL circuit”), and is not reset during the start-up process of the semiconductor integrated circuit. The PLL circuit in the internal clock generating circuit 400 outputs the internal clock signal ICLK after coincidence between the external clock signal ECLK and the internal clock signal ICLK. The control circuit 300 outputs a control signal CON in order to control a memory circuit of the semiconductor memory device in accordance with the power supply voltage Vcc, the internal power supply voltage IVcc and the internal clock signal ICLK. The control circuit 300 is reset by the power-on reset signal POR as well as the internal voltage generating circuit 200.
Each of the internal voltage generating circuit 200 and the control circuit 300 has an input set-reset circuit which is reset by the power-on reset signal POR. The input setting circuit is a flip-flop circuit which is reset when the power-on reset signal POR is kept in “Low” (hereinafter referred to as “L”) level and is set when the power-on reset signal POR is kept in “High” (hereinafter referred to as “H”) level. The input set-reset circuit in the control circuit 300 has circuitry 810 and an internal circuit 820 as shown in FIG. 2B. The circuitry 810 has two NAND circuits NA81 and NA82 and two inverters IV81 and IV82. The NAND circuit NA81 receives the internal clock signal ICLK and an output signal from the NAND circuit NA82. The inverter IV82 receives the power-on reset signal POR. The NAND circuit NA82 receives output signals from the NAND circuit NA81 and the inverter IV82. The inverter IV81 is coupled between the NAND circuit NA81 and the internal circuit 820. When it is necessary that a level on a node nd81 is kept in the “H” level by default configuration, the power-on reset signal POR has to turn to the “H” level when the internal clock signal ICLK is kept in the “H” level. Also, FIG. 2C is a block diagram for describing the PLL circuit 700 in the internal clock generating circuit 400. The PLL circuit 700 has a phase comparator 710, a charging pump 720, a loop filter 730, a voltage-controlled oscillator 740 and a frequency divider 750 coupled in series. When the power supply voltage Vcc is generated, the PLL circuit 700 operates so that a divided frequency clock signal DCLK can coincide in a phase with the external clock signal ECLK. After the coincidence between the phases of the divided frequency clock signal DCLK and the external clock signal ECLK, the internal clock signal ICLK output from a voltage-controlled oscillator 740 is stabilized.
FIGS. 3(a) through 3(e) are signal waveform diagrams for describing a reset operation of the semiconductor integrated circuit in FIG. 1. FIG. 3(a) represents a waveform of the power supply voltage Vcc, FIG. 3(b) represents a waveform of the power-on reset signal POR, FIG. 3(c) represents a waveform of the internal power supply voltage IVcc or the control signal CON, FIG. 3(d) represents a waveform of the external clock signal ECLK, and FIG. 3(e) represents a waveform of the internal clock signal ICLK. After the power supply voltage Vcc is generated as shown in FIG. 3(a), the power-on reset signal POR is turned from the “L” level to the “H” level as shown in FIG. 3(b). The internal power supply voltage IVcc or the control signal CON, which was indeterminate before the power supply voltage Vcc is generated, is determined by being reset in accordance with the rising edge of the power-on reset signal POR as shown in FIG. 3(c). On the other hand, after the power supply voltage Vcc is generated, the internal clock signal ICLK, which was indeterminate before the power supply voltage Vcc is generated, is determined in accordance with the coincidence in the phases between the external clock signal ECLK and the divided frequency clock signal DCLK as shown in FIG. 3(e).
In addition, other semiconductor integrated circuits have been proposed as described in a Document 1 (Japanese Patent Publication Laid-open No. 2000-299436) and a Document 2 (Japanese Patent Publication Laid-open No. 2002-50200). These semiconductor integrated circuits have a latch circuit which is connected with an internal circuit, and the latch circuit can reset the internal circuit when the power supply voltage is generated.
However, it takes a long time for the internal clock signal ICLK to be determined in the PLL circuit 700 of the internal clock generating circuit 400 as described above. When the internal clock signal ICLK is determined after the timing of the rising edge of the power-on reset signal POR, at which the internal power supply voltage IVcc or the control signal CON is determined, the node nd81 of the control circuit 300 may not be kept in the “H” level by the default configuration. That is, the control circuit 300 may not be properly reset because the indeterminate internal clock signal ICLK is input to the control circuit 300. As stated above, in the semiconductor integrated circuit of the prior art which includes an internal circuit which needs not to be reset when the power supply voltage Vcc is generated (for example, the internal clock generating circuit 400), another internal circuit which operates based on an output signal from the internal circuit and which needs to be reset when the power supply voltage Vcc is generated (for example, the control circuit 300), and the other internal circuit which needs to be reset when the power supply voltage Vcc is generated (for example, the internal voltage generating circuit 200), these internal circuits, which need to be reset when the power supply voltage Vcc is generated, are reset by the same power-on reset signal in accordance with the rising edge of the power supply voltage Vcc. Hereupon, the another internal circuit operates based on the output signal from the internal circuit which needs not to be reset when the power supply voltage Vcc is generated. That is, the other internal circuit may receive the output signal from the internal circuit ahead of the power on reset signal. Therefore, on such an occasion as this, the other internal circuit may not be properly reset.